I encountered a problem in Verilog-XL: failed generation of netlist due to undefined models (re-phrased).
SOLUTION: search parent directories for presence of .cdsinit and remove/rename/edit to avoid redefinition of libraries and paths upon starting the Cadence.
Hope this helps whoever has the same issue (primarily those who used their account for other projects)
2 comments:
I encountered a problem in Verilog-XL: failed generation of netlist due to undefined models (re-phrased).
SOLUTION: search parent directories for presence of .cdsinit and remove/rename/edit to avoid redefinition of libraries and paths upon starting the Cadence.
Hope this helps whoever has the same issue (primarily those who used their account for other projects)
Hi Kiril;
I did as you said, and nothing changed, couldn't get it working in Verilog.
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